vllm.models.minimax_m3.nvidia.ops.gather_nvfp4_index_k
¶
Gather NVFP4 index-K pages into compact FP8 pages for the Q8KV8 prefill indexer.
A packed NVFP4 page [128, 72] holds the E2M1 codes of all 128 tokens (64 B
per token, low nibble first) followed by their E4M3 16-element block scales
(token * 8 + group), with no global scale. Each element dequantizes to
e4m3_rn_satfinite(e2m1 * scale), the value the Q8KV4 decode indexer scores,
so prefill and decode rank pages from identical keys.
Where Triton can emit it, each four elements are one QMUL4
(mul.rn.satfinite.e4m3x4.e2m1x4.e4m3x4), the instruction the decode kernel
dequantizes with; otherwise the product is formed exactly in fp32 and rounded
once, which gives the same bytes.
Functions:
-
minimax_m3_gather_nvfp4_index_k_fp8–Dequantize each request's leading NVFP4 pages into contiguous FP8 pages.
_qmul4_supported(device_index)
cached
¶
Whether Triton emits PTX that can use QMUL4 on this device.
Triton takes the PTX ISA version from its Blackwell ptxas: the bundled one
unless TRITON_PTXAS_BLACKWELL_PATH points at a CUDA 13.4+ ptxas.
Source code in vllm/models/minimax_m3/nvidia/ops/gather_nvfp4_index_k.py
minimax_m3_gather_nvfp4_index_k_fp8(kv_cache, block_table, num_pages, page_offsets, max_num_pages, out)
¶
Dequantize each request's leading NVFP4 pages into contiguous FP8 pages.
Parameters:
-
(kv_cache¶Tensor) –[num_blocks, 128, 72]uint8 packed NVFP4 pages. -
(block_table¶Tensor) –[num_reqs, max_blocks]int32 physical page ids. -
(num_pages¶Tensor) –[num_reqs]int32 pages to gather per request (its firstnum_pages[r]logical pages). -
(page_offsets¶Tensor) –[num_reqs]int32 first output page of each request. -
(max_num_pages¶int) –Host upper bound of
num_pages. -
(out¶Tensor) –[>= sum(num_pages), 128, 128]contiguous float8_e4m3fn.
Returns:
-
Tensor–out.